See the failure before the board is built

This demo shows a KiCad netlist-derived voltage mismatch and a metadata-based I2C address conflict that can slip past normal schematic and PCB checks.

Example project input

KiCad netlist-derived check

Failing

$ cd demos/overvoltage_rule/kicad
$ rv scan .

netlist: demos/overvoltage_rule/kicad/overvoltage_pro.net

nets:
  - /+5V
  - /+3V3
  - GND

component_limits:
  - ref: U1
    pin: 1
    net: /+5V
    max_voltage: 3.30

Architon-style scan output

Deterministic rule result

FAIL

ARCHITON SCAN
Target: .
Result: FAIL — scan violations detected
Parts: 3
Nets: 3
Errors: 1
Warnings: 0
Rules: 1
Violations: 1

Rule findings:
- ERROR RULE_OVERVOLTAGE: U1 pin 1 on net /+5V is 5.00V (max 3.30V)

Detected Netlist: demos/overvoltage_rule/kicad/overvoltage_pro.net
Wrote architon-report.json
exit code: 2
scan completed with 1 violation(s); wrote architon-report.json

This check runs directly on the KiCad netlist. Voltage is inferred from net names and component limits.

What is being checked

The layout can be valid while the system assumption is wrong.

A PCB DRC can confirm trace clearance and geometry. A schematic ERC can confirm pin categories and connectivity. Architon checks whether the connected rails, components, and interfaces are compatible at the architecture level.

Get started locally

Run the CLI against a real hardware project.

Try the CLI on GitHub Request early access